Bensley Platform -- The Architectural overview of the Platform:

The Architectural overview of the Platform

• The MCH connects up to 16 fully buffered DIMMs (four memory channels with upto four DIMMs per channel).
• This provides 8.5GB/s of write memory bandwidth and 17 GB/s of read memory bandwidth when DDR2 533MHz memory is used and when DDR2 667 MHz memory is used, the write bandwidth can be 10.7 GB/s and the read bandwidth  can be 21.3GB/s.
• In Fully Buffered DIMM read and the write operation can be done simultaneously, so the total memory bandwidth is 25.5GB/s for 533MHz and the 32.0GB/s for 667MHz.
• The MCH can provide a maximum of six x4 PCI Express interface and one x4 ESI interface to the ESB2.
• It is also possible to configure certain x4 interface pairs into a single x8 interface.
• Each PCI Express port on the MCH provides 4GB/s bidirectional bandwidth when configure as an x8 port or 2GB/s bidirectional bandwidth when configured as an x4 port. 
• In addition to these performance features, Bensley platforms also provide a wide range of RAS features such as memory interface ECC, x4/x8 single Device Data correction, CRC, Parity protection, out of band via SMBus, memory mirroring , memory sparring and Hot plug support on PCI Express interface.