Bensley Platform -- The Architectural overview of the Platform:

The Architectural overview of the Platform

• Let's take for our Illustration, an Architecture compromising the Blackford chipset (North Bridge) with the South Bridge, ESB2.
• Here the Blackford chipset is paired with the Dempsey processor and is comprised of the Blackford Memory controller Hub (MCH), the Enterprise south Bridge 2(ESB2) and the I/O system.
• This MCH is configured for symmetric multiprocessing across two independent front side bus interface that connect to the Dempsey processor.
• This dual Independent bus architecture gives an improved performance by allowing increased front side bus speeds and Bandwidth.
• Each front side bus on the MCH can operate at 64bit wide and the maximum of 1333 FSB (In case of Woodcrest Processor and 1066 FSB in case of Dempsey Processor) data bus and capable of transferring data at 8.5GB/s for a total bandwidth of 17GB/s.
• The MCH supports a 36-bit wide address bus, capable of addressing upto 64GB of memory